1. Field of the Invention
The present invention relates to a bipolar transistor design, and, in particular, to a process for forming a vertically isolated bipolar device that can be incorporated into a CMOS process flow with a minimum number of additional steps.
2. Discussion of the Related Art
FIG. 1 shows a cross-sectional view of a conventional vertical PNP bipolar transistor structure. Conventional PNP bipolar transistor structure 100 is formed in P-well 102. P-well 102 is created within P-type silicon substrate 104. The collector of bipolar transistor 100 is formed by P-well 102 and buried P+ layer 106. Buried P+ layer 106 is connected to collector contact 108 by P+ sinker structure 110. Collector contact 108 and P+ sinker 110 are electrically isolated from the base and emitter by intra-device isolation structure 112.
The base of bipolar transistor 100 is formed by N-type layer 114 having N+ base contact region 116. N+ base contact region 116 is self-aligned to oxide spacer 118 formed on sidewall 120a of extrinsic P+ polysilicon emitter 120. Polysilicon emitter contact component 120b of diffused polysilicon emitter structure 120 overlies P+ single crystal emitter component 120c. Polysilicon emitter contact component 120b of diffused polysilicon emitter 120 is separated from base 114 by dielectric layer 124.
Older IC designs tended to use only bipolar transistors of the same type, for example exclusively PNP or NPN. In such circuits, it was possible for the transistors to share a common collector biased at a constant value. However, the ever-increasing demand for faster processing speeds and enhanced flexibility has dictated that PNP and NPN bipolar transistors be utilized together in the same circuit, and that they be employed in conjunction with MOS transistors. As a result, it has become increasingly important to electrically isolate individual bipolar devices formed within the same silicon substrate.
One way of providing such isolation is through silicon-on-insulator (SOI) technology. FIG. 2 shows a vertical PNP bipolar transistor 200 formed in an SOI isolation scheme.
PNP bipolar transistor 200 is similar to bipolar transistor 100 of FIG. 1, except bipolar transistor 200 is laterally isolated from adjacent semiconducting devices by dielectric-filled trenches 202. PNP bipolar transistor 200 is vertically isolated from underlying P-type silicon 204 by buried oxide layer 206.
SOI isolated bipolar transistor 200 of FIG. 2 is suitable for a number of applications. However, this design suffers from the serious disadvantage of being relatively difficult and expensive to fabricate. Specifically, formation of buried oxide layer 206 within underlying P-type silicon 204 entails complex processing steps which substantially elevate cost.
One way of forming buried oxide layer 206 is high-energy ion implantation of oxygen into the underlying silicon, followed by oxidation. The expense of this step is attributable to the complex ion implantation equipment required, and the difficulty of ensuring complete oxidation deep within the silicon.
An alternative way of forming the buried oxide layer is to join oxide surfaces of two separate silicon wafers, and then remove backside silicon of one of the wafers to produce a surface suitable for epitaxial growth. The high cost of this process is associated with the difficulty in effectively bonding together the oxide surfaces to form an single integrated wafer structure that is substantially free of defects.
Many other methods exist for forming a buried oxide layer in addition to the those specifically described above. However, these processes are also fraught with the potential for error, resulting in increased defect densities and high production costs.
Therefore, it is desirable to utilize a process flow for forming a vertically isolated bipolar transistor device compatible with CMOS processes which minimizes both the number and cost of additional processing steps.
The present invention proposes a vertically isolated bipolar transistor structure, and a process flow for forming that structure, which utilizes a an implanted isolation layer formed underneath the collector. This vertical junction isolation scheme eliminates processing hurdles inherent in formation of a buried oxide layer between the collector and the underlying silicon. When employed in conjunction with trench lateral isolation, the isolation layer may be formed as a blanket implant, thereby avoiding a masking step.
A method of electronically isolating a bipolar transistor device from an underlying semiconductor material in accordance with the present invention comprises providing an isolation layer of dopant of a first conductivity type in the semiconductor material underneath a collector of a second conductivity type opposite the first conductivity type.
A process flow for forming a bipolar structure in accordance with one embodiment of the present invention comprises the steps of performing an isolation implant of dopant of a first conductivity type into a semiconductor substrate to form an isolation layer, and then thermally driving the isolation implanted dopant into the substrate. Next, a first masked buried layer implant of dopant of the first conductivity type into the semiconductor substrate to form a first buried layer is performed. A second masked buried layer implant of dopant of the second conductivity type into the semiconductor substrate outside of the first buried layer to form a second buried layer is then performed. Additional lightly doped semiconductor material of the first conductivity type is created on top of the substrate, and a first sinker of the first conductivity type extending from a surface of the additional semiconductor material to the isolation layer is formed. A second sinker of the second conductivity type extending from the surface of the additional semiconductor material to the second buried layer is formed. A first well implant of dopant of the second conductivity type into the additional semiconductor material above the second buried layer to form a first well is performed, the first well including the second sinker. Finally, a base region of the first conductivity type is formed within the first well, and an emitter of the second conductivity type is formed within the base region.
A bipolar device in accordance with one embodiment of the present invention comprises a semiconductor material of a first conductivity type having a surface, a well of the first conductivity type formed in the semiconductor material and having a bottom portion at a first depth in the semiconductor material, and an isolation layer of a second conductivity type opposite the first conductivity type positioned in the semiconductor material beneath the well. A buried collector layer of the first conductivity type is positioned in the bottom portion of the well above the isolation layer. A base region of the second conductivity type is positioned inside the well and extends from the surface of the semiconductor material to above the buried collector region, and an emitter of the first conductivity type is positioned within the base.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth illustrative embodiments in which the principles of the invention are utilized.